1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device including a multi-timing controller that produces a timing signal according to each display standard from a control signal according to various standards to drive the liquid crystal display device.
2. Description of the Related Art
Generally, a liquid crystal display device has an inherent resolution corresponding to the number of integrated pixels, and has a higher resolution as its dimension becomes larger. In order to display a high quality of picture, makers of the liquid crystal display device increases a pixel integration ratio within a liquid crystal panel between liquid crystal display devices with same dimension to differentiate the resolution.
The standards of the image signal and the control signals under circumstance of a personal computer, etc. including the liquid crystal display device along with the resolution are set by the Video Electronics Standard Association (VESA) on February, 1989.
The typical standards of displays being commercially available in the current display industry include DOS Mode(640×350, 640×400, 720×400), VGA(640×400), SVGA(800×600), XGA(1024×768), SXGA(1280×1024) and UXGA(1600×1200) Modes, etc.
The LCD has a resolution fixed by the number of arranged pixels and hence requires image signals corresponding to a resolution of the liquid crystal display panel and control signals thereof from the system. Accordingly, the system converts image signals and control signals corresponding to various display standards into image signals and controls signals complying with a resolution and a display standard of the LCD using a scaler chip and the like to apply the same to the LCD.
FIG. 1 is a block diagram showing a configuration of the conventional LCD. In FIG. 1, an interface part 10 receives a data (RGB data) and control signals (e.g., an input clock, a horizontal synchronizing signal, a vertical synchronizing signal and a data enable signal) to apply them to a timing controller 12. A low voltage differential signal (LVDS) interface and a transistor transistor logic (TTL) interface are largely used for a data and control signal transmission to the driving system. Such interfaces are integrated into a single chip along with the timing controller 12 by collecting each function of them.
The timing controller 12 takes advantages of a control signal inputted via the interface part 10 to produce control signals for driving a data driver 18 consisting of a plurality of drive IC's (not shown) and a gate driver consisting of a plurality of gate drive IC's (not shown). Also, the timing controller 12 transfers data inputted from the interface part 10 to the data driver 18. A reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the data driver 18, which are established by a producer on a basis of a transmissivity to voltage characteristic of the panel. The data driver 18 selects reference voltages in accordance with an input data in response to control signals from the timing controller 12 to convert the same into an analog image signal and apply the converted signal to a liquid crystal panel 22. The gate driver 20 makes an on/off control, one line by one line, of gate terminals of thin film transistors (TFT's) arranged on the liquid crystal panel 22 in response to the control signals inputted from the timing controller 12. Also, the gate driver 20 allows the analog image signals from the data driver 18 to be applied to each pixel connected to each TFT. A power voltage generator 14 supplies an operation voltage to each element, and generates a common electrode voltage and applies it to the liquid crystal panel 22.
In the configuration as mentioned above, the timing controller 12 produces desired control signals for a driving of the LCD in response to the input control signals. In this case, the timing controller 12 generally counts a clock on a basis of the edge of a horizontal synchronizing signal Hsync or a data enable (DE) signal to generate a control signal. The output signals of the timing controller 12 have a difference from each other depending on types of data drive IC and gate drive IC.
Hereinafter, types and timing of control signals used commonly except for signals required specially will be described. First, control signals required for the data driver includes source sampling clock (SSC), source output enable (SOE), source start pulse (SSP), liquid crystal polarity reverse (POL), a data polarity selection or data reverse (REV) and odd/even pixel data signals, etc. The SSC signal is used as a sampling clock for latching a data in the data driver, and which determines a drive frequency of the data drive IC. The SOE signal transfer data latched by the SSC signal to the liquid crystal panel. The SSP signal is a signal notifying a latch or sampling initiation of the data during one horizontal synchronous period. The POL signal is a signal notifying the positive or negative polarity of the liquid crystal for the purpose of making an inversion driving of the liquid crystal. The REV signal is a signal selecting the polarity of the transferred data. The odd/even pixel data signal is a signal representing an odd data of odd-numbered pixels and an even data of even-numbered pixel.
An operation of the data driver receiving the above-mentioned control signals is shown in FIG. 2. Referring to FIG. 2, first, if the data driver recognizes a “high” input of the SSP at the rising or falling edge of the SSC, then it latches a data inputted in response to the SSC. Next, the latched data is decoded into an analog output voltage in response to the SOE and supplies it to the liquid crystal panel. At this time, a positive decoder output voltage higher than the common electrode voltage is selected when the POL signal is a “high” state; while a negative decoder output voltage lower than the common electrode voltage when the POL signal is a “low” state, thereby making an inversion drive of the liquid crystal panel into a positive/negative polarity.
Control signals required for the gate driver includes gate shift clock (GSC), gate output enable (GOE) and gate start pulse (GSP) signals, etc. The GSC signal is a signal determining a time when a gate of the TFT is turned on or off. The GOE signal is a signal controlling an output of the gate driver. The GSP signal is a signal notifying a first drive line of the field in one vertical synchronizing signal.
An operation of the gate driver receiving the above-mentioned control signals is shown in FIG. 3. Referring to FIG. 3, the gate driver recognizes a “high” state of the GSP signal at the rising or falling edge of the GSC signal to output a gate signal maintaining a “high” state during a time interval equal to one period of the GSC signal. At this time, the GOE signal is combined with the gate signal output to disable an output equal to a “high” width of the GOE signal.
As described above, such a LCD requires individual controllers generating the control signals for controlling the data driver and the gate driver from the image signals and the control signals inputted in response to its inherent resolution. However, since the LCD uses various display formats from the VGA mode until the UXGA mode, it requires various timing controllers according to each resolution thereof. For this reason, the conventional LCD has a problem of a cost rise according to a development of the timing controller. In addition, the conventional LCD has a problem in that one developed timing controller can not be used for a liquid crystal display device according to a different display standard.